1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) manufacturing method and device, and more particularly, a semiconductor IC device and manufacturing method for forming insulation layers by varying the carbon content therein.
2. Discussion of the Background
In a high-speed, high-functional conventional electronic circuit, highly independent and different functions, such as memory and logic, have been integrated on a large scale on different semiconductor substrates. Each of the semi-conductor substrates is arranged on an insulated circuit board if required and is connected with metal interconnects. However, the lengths of metal interconnects formed on the insulated circuit board are much longer than the dimensions of an electronic element formed on the individual semiconductor substrates. Floating capacitance between surrounding insulating substances causes a large wiring delay. Therefore, such conventional technology is not suited for high-speed signal transmission between electronic elements on different semiconductor substrates. If the number of signal lines for a bus connecting different semiconductor substrates needs to be increased, the load capacitance of the bus increases; this increase in load capacitance degrades the noise resistance of the buffer circuit which drives the bus, causing erroneous operations to occur.
To resolve this problem and to provide a high-speed, and highly functional, electronic circuit, there is a growing demand for a monolithic IC which includes a plurality of electronic circuits formed on the same semiconductor substrate and having mutually fundamentally different functions. An example is an integrated system in a single-chip microcomputer and the like, comprising a central processor unit (CPU), which has a computing function, a memory, and a peripheral interface.
However, integrating a system on a single chip has some problems. For example, a metal-insulation-semiconductor field-effect transistor (MISFET), that constitutes a memory cell in a memory circuit, and a MISFET, that constitutes a logic circuit, have different threshold settings. Because of this difference in threshold settings, the different MISFETS are manufactured to have different gate-insulation layer thicknesses, substrate dopant concentrations, and the like during manufacturing steps. Differences in the functions of the MISFET used for the memory cell and the MISFET used for the logic circuit and the resulting different conditions are described in more detail below.
A memory cell, such as a dynamic random access memory (DRAM), comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), which has a silicon dioxide (SiO.sub.2) layer for the insulation layer, and also comprises capacitors, which are connected to the MOSFETs. The threshold voltage of a MOSFET cannot be set low because leakage current must be suppressed when the word line connected to the gate electrode of the MOSFET is turned off and electric charge stored in the capacitor must be retained. Especially when many uniform elements are integrated on the same substrate, the dopant concentration of the channel portion directly below a gate must be set high to suppress the short-channel effect which causes gate length dependency on threshold voltage. The gate length is the distance between source and drain electrodes.
In the memory cell, a voltage that is higher than the cell-array voltage (which is applied to the source electrode when the capacitor is charged) by at least the threshold voltage is applied to the word line. As described above, the threshold voltage for the MOSFET of the memory cell is also set high. Therefore, a large voltage is applied to the gate-oxide layer while the capacitor is being written. To prevent leakage current due to a high-voltage application or degradation of the gate-oxide layer, it is necessary that the electric field from the gate-oxide layer be kept small; that is, the gate-oxide layer must be made thick as described above. In an example of a conventional memory cell, the gate length is 0.35.mu.m, the cell-array voltage is 2.5V, the threshold voltage is 1.2V, and a voltage of 4.0V or larger is applied to the word line. To resist the electric field generated by the above, the gate-oxide layer must be approximately 10 nm thick.
In contrast to a memory cell, a MOSFET in logic circuit is not affected by leakage current, and it is desirable that the threshold voltage be set as low as possible to promote high-speed operation and sufficient driving capability.
Also, at certain levels, the short-channel effect does not affect the logic circuit performance, and it is desirable that the substrate dopant concentration in the channel portion be maintained as low as possible.
Further, the gate-oxide-layer thickness of the MOSFET in the logic circuit must be as thin as possible to obtain a sufficient driving capability. When the actual gate length is 0.35.mu.m for the logic circuit, as is standard, the commonly used threshold voltage is approximately 0.7V and the oxide-layer thickness is approximately 7 nm.
As described, to form MOSFETs with different threshold voltages, that is, with different channel concentrations and different gate oxide-layer thicknesses, a series of plural steps are performed to obtain each of the MOSFETs, thus increasing the manufacturing cost, which is disadvantageous. Even when oxide layers of the same thickness are made, if a part of them is thinned by an etching solution, such as an HF solution, a new pattern must be formed to protect the portion which needs to maintain the original oxide-layer thickness.
A technique introduced to resolve these problems replaces the logic MOSFET with the memory cell MOSFET so that the gate-oxide layers can have a single thickness. The threshold voltage for the memory cell decreases. As a result, a leakage current (negative voltage) tends to flow when the word line is off. This problem is avoided by applying a negative voltage to the word line when it is turned off, if the memory cell MOSFET has an n-type channel (T. Tsuruda et al., IEEE 1996, Custom Integrated Circuit Conference, No. 13.2).
However, in order to apply a negative voltage to the word lines whenever they are off, a voltage source circuit with large driving power is required, and the power must be supplied to fulfill the demand even during stand-by time. Even when the data are not exchanged, when the work line is off, the low-voltage circuit nonetheless still consumes some power. This situation is contradictory to the purpose of reducing power consumption. For example, a low-power electronic circuit is essential for portable compact information terminals and the like, but it is difficult to provide the low-power circuit with this method.
In addition, the gate-oxide layer of a MOSFET for the memory cell is made as thin as that of the MOSFET for the logic circuit. Unlike conventional technology, this arrangement makes it impossible to boost the word line over cell-array voltage by more than the threshold voltage. As a result, when the electric charges that can be stored in the memory cell decrease, frequent refreshing is needed, and power consumption increases, which is problematic.
Also, in a field-effect transistor (FET) using a polysilicon layer as a gate electrode to which boron atoms are added, boron penetration phenomena, in which boron atoms in the gate electrode penetrate to a channel region, (i.e., semiconductor substrate surface or SOI surface via the gate-insulation layer) is a problem. Penetration of boron atoms to the channel region changes the channel-dopant concentration, which determines the threshold voltage and the like; this phenomena makes it difficult to obtain device properties as desired or causes un-desirable variation in properties among integrated devices.
In addition, to achieve a high-speed and highly functional, electronic circuit, in large-scale integration (LSI) specifically, there is a growing demand for miniaturization of FETs, which are a major constituent of LSI. However, miniaturization of the FETs has the difficulties described below.
For example, if the channel length is reduced, a short-channel effect is induced in which the threshold voltage decreases with the decrease of the channel length. The short-channel effect is caused by the distortion of the electric field at a region abutting the source or the drain-electrode to the channel portion. If a device has a different threshold voltage from the one intended in the design of the device, the device may not behave accurately as intended, degrading the function of the overall IC. Also, the threshold voltage is dependent on the dimensions of a gate electrode. A little variation of the gate electrode length can cause the device to lack the desired properties. This low tolerance is a drawback for semiconductor IC manufacturing in which many uniform devices are desired.
The short channel effect can be avoided by locating the position of the pn junction, which forms the junction between a source/drain electrode(s) and the semiconductor substrate, closer to the substrate surface. However, by shortening the depth of the pn junction, the resistivity of the source/drain electrode(s) which is constructed with the pn junctions, increases; this arrangement impedes the high-speed signal transmission through the device.
On the other hand, if the dopant concentration of a silicon substrate is increased along with the miniaturization of the device, the thickness of the depletion layer, extending from the pn junction surface, decreases and the leakage of the pn junction increases. Also, with a shallow pn junction, if the contact for electrical connection with the metallic wirings is formed on the surface in the source/drain electrodes, metallic substances diffuse downward to penetrate the pn junction and unfavorably induce leakage from the junctions.
In addition to lowering the source/drain electrode resistance, the surface of the dopant region may be combined with a metal (e.g., being combined with a silicon substrate is referred to as "to become silicide"). However, if the pn junction is shallow, metallic atoms diffuse through the dopant region to reach the pn junction surface, causing leakage from the junction. If a current leakage occurs through the junction, the device behaves incorrectly. A memory device, such as a DRAM, may lose the recorded data, and thereby lose the fundamental function as a memory device.
FIG. 15 is a cross-sectional view of a conventional elevated source drain type MOSFET formed using conventional technology. A technique proposed to resolve these problems additionally selectively grows silicon epitaxial layers 12a, 12b on the projected source/drain electrodes on the main surface of a silicon substrate 10. The surface of the silicon epitaxial layers 12a, 12b is moved above a surface region (region C in which a channel is formed) of the silicon substrate 10. Dopant regions 14a, 14b are formed below the substrate surface to pull down the pn junction. The source/drain electrodes 15a, 15b may provide sufficient thickness to prevent resistance increases, while the pn-junction position is close to the channel surface (IEEE Electron Device Letters, Vol. 11, No. 9, September 1990, pp. 365-367).
However, in this method, the location of the final pn junction of a source/drain electrode(s) must be adjusted precisely relative to the channel surface of the silicon substrate 10.
If the junction is too shallow from the desired location, the current driving force of this MOSFET is significantly decreased. If the junction is too deep from the desired location, the short-channel effect becomes a problem. However, the epitaxial layer growth by the epitaxial growth method is sensitive to the surface conditions on which selective epitaxial growth takes place. For example, the film thickness of the silicon layers 12a, 12b or film quality (presence/absence of defects) varies according to the surface roughness, shape, and crystal-lattice structure of the substrate 10 underneath. The presence of a natural oxide layer on the surface of the substrate 10 before epitaxial growth and the presence of defects introduced during the gate-electrode processing causes the film thickness and the film quality of the silicon layers 12a, 12b to vary from device to device.
As described, if the film thickness of the silicon layers 12a, 12b is not uniform, it becomes difficult to form the pn junction at the desired depth. Dopant, which forms the source/drain electrodes, is introduced from the surface of the silicon layers 12a, 12b to the surface of the substrate 10, and therefore, the junctions are formed at a predetermined distance from the surface of the silicon layers 12a, 12b. Thus, if the film thicknesses of the silicon layers are not uniform, it becomes difficult to locate the junction at a desired position. In addition, the presence of crystalline defects induces transient enhanced diffusion generation, Unexpected diffusion may result even if a given dopant thermal diffusion is provided. Therefore, it is virtually impossible to obtain uniform junction depths over a large number of devices.
To avoid these problems, before adding a silicon layer 12a, 12b onto a substrate 10, ions are implanted at a low acceleration energy on the surface region of silicon substrate 10. However, decrease of accelerating voltage of ion implantation decreases the ion-implantation rate. Because ions must be implanted at a high concentration to obtain an excellent conductivity, the implantation process takes an extremely long time which affects manufacturing productivity. Also, epitaxial growth following this procedure is dependent on the conductivity type of the source/drain electrode(s). When manufacturing a complementary MOSFET (CMOS circuit), films of different properties may be fabricated. Furthermore, the shallow junction fabricated above makes it impossible to perform high-temperature thermal treatment, and the like, following manufacturing process steps, in which the junction depth is changed.
Crystalline defects which are caused during the ion implantation or the formation of the gate-oxide layer can accelerate the dopant-diffusion process. Even in a low temperature processing which does not cause any problems in general, an unexpectedly deep junction can be created because it is difficult to control the junction depth. As a result, a stringent specification is required for thermal processes for the following purposes which limits the type of thermal processing available: for recovering crystalline defects; for electrical activation of implanted ions; and for formation and thermal processing of an interlayer insulator.
As described in detail herein, when forming electronic circuits having different functions, such as a memory function and a computing function, on the same semiconductor substrate (one-chip), it is difficult to fulfill the requirements needed for each of the MOSFETs which constitute circuits of different functions. For example, the channel portion of a MOSFET for a memory circuit has a high-dopant concentration and it must have a thick gate-oxide layer. On the other hand, the channel portion of a MOSFET for a logic circuit desirably has a low-dopant concentration and a thin gate-oxide layer. Therefore, in order to monolithically form circuits of different functions on the same substrate, a plurality of types of gate-oxide layers must be formed which increases the number of manufacturing steps, such as the addition of an oxidation step, and increases cost.
To resolve the problems, there is a technique in which a negative voltage is applied onto the word line which is turned off in order to use a MOSFET of a logic circuit as that of a memory circuit. However, this technique increases power consumption which is undesirable.